This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.11-375860, filed Dec. 28, 1999; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention is related to a test vector generation method and a program for automatically generating test vectors for use in testing whether or not instructions are implemented in a processor in agreement with the predetermined specifications of the instruction set architecture (ISA), and a test method and a chip manufacturing method making use of the test vectors as generated by the test vector generation method.
2. Description of the Related Art
In the past, the operation of a processor has been tested to confirm implementation of instructions in the processor in agreement with the predetermined specification, for example, (1) by manually preselecting a variety of combinations of operand values and handcoding test vectors with the combinations, or (2) by automatically generating combinations of operand values at random and then generating test vectors with the combinations. However, in accordance with the above described method (1), a considerable time is required for generating test vectors. On the other hand, in accordance with the above described method (2), a considerable time is required for completing a test program because the reliability of test program must be enhanced by making use of a large number of combinations of test vectors while each combination can be easily generated.
It is an object of the present invention to provide a method and a program for automatically generating test vectors with which a reliable test can be completed within a short time, and a test method and a chip manufacturing method making use of the test vectors as generated by the test vector generation method.
In order to accomplish the objects as described above, in accordance with the first feature of the present invention, a method for automatically generating test vectors for use in testing a processor as to whether or not instructions in the processor are implemented in agreement with the predetermined specifications includes an ISA specification analysis step of analyzing specifications of an instruction set architecture (ISA) of the processor; a test vector generation data preparation step of preparing data required for generating test vectors; and a test vector generation step of generating test vectors by the use of said data.
The ISA specification analysis step includes a step of determining conditions, which the set of the source operands and the result of execution of an instruction must satisfy in order not to invoke an exception of the processor under test, by the use of operand information, operation description and mnemonics. The test vector generation data preparation step includes a step of generating a set of source operand values satisfying both the two conditions of the condition which the set of the source operands must satisfy and the condition which the result of execution of an instruction must satisfy. The test vector generation step may include a step of expanding the instruction under test with an argument of source operand values satisfying said two conditions.
It is possible to separately test the operation of a respective instruction itself by automatically generating operand values which invoke no exception.
The ISA specification analysis step may include a step of analyzing a conditional expression to be satisfied by operand values as input or satisfied by the result of the execution of an instruction in order to confirm if the conditional expression can inherently not be TRUE or can inherently not be FALSE.
It is therefore possible to detect a bug in the ISA specifications by analyzing a conditional expression in order to confirm if the conditional expression can inherently not be TRUE or can inherently not be FALSE.
The test vector generation method may further include a compare instruction sequence adding step of generating an expected value to be output when the processor under test performs a correct operation and adding an instruction sequence for comparing said expected value to the output value as actually output from the processor under test.
It is possible to test the circuit on the register transfer level (RTL) even without an instruction level simulator by comparing the expected value with the value as actually output.
The test vector generation method may further include an execution instruction counting step of counting, in the case that an instruction to be tested is a branch instruction, the number of instructions to be executed if the branch is not taken and the number of instructions to be executed if the branch is taken; a taken/not taken branch counting step of counting, among from sets of the source operand values satisfying said two conditions, the number of sets of the source operand values with which the branch is not taken and the number of sets of the source operand values with which the branch is taken; and a step of obtaining the sum of the product of the number of instructions to be executed if the branch is not taken and the number of sets of the source operand values with which the branch is not taken and the product of the number of instructions to be executed if the branch is taken and the number of sets of the source operand values with which the branch is taken.
The estimation of the time required for executing test vectors becomes possible by calculating the number of cases that the branch is not taken and the number of instructions to be executed when the branch is not taken and, in the same manner, calculating the number of cases that the branch is taken and the number of instructions to be executed when the branch is taken.